1. Field of the Invention
The present invention relates to a semiconductor device employing a shallow trench isolation structure (STI) as an element isolating structure and a method of fabricating the semiconductor device.
2. Description of the Related Art
A technique of isolating elements has recently been changing from local oxidation of silicon (LOCOS) to shallow trench isolation (STI) for the purposes of high integration and miniaturization in the fabrication process of semiconductor memory devices. In the element isolation technique employing STI, shallow trenches are formed and filled with an isolator so as to be flattened, whereupon a trench isolating region is provided.
Furthermore, in the element isolating technique employing STI, the trench isolating region is set so as to have a minimum width in a region of a memory cell. With this, a depth of the trench isolating region is reduced in order that a filling capacity of the trench isolating region may be ensured in the aforesaid region of the memory cell, whereby an aspect ratio is required to be reduced as much as possible in filling the trench isolating region.
However, a peripheral circuit performing drive control of the memory cell includes elements which are required to have a higher breakdown voltage than those in the memory cell. Accordingly, when the aforesaid trench isolating region is employed, the distance of isolation between elements or the width of the trench isolating region is increased or a stopper region is formed under the trench isolating region. However, either method requires a large width of trench isolating region in order that a large element isolation width may be ensured or a stopper region may be formed, resulting in a problem that an area for the element isolation is increased.
To overcome the above-described problem, JP-A-2002-368077 discloses a structure in which the depth of the trench isolating region of the peripheral circuit is larger than a depth of a diffusion region of a cell array. As the result of the structure, since the trench isolating region with a depth in accordance with the breakdown voltage is formed, an increase in the area of the cell is limited and the breakdown voltage can reliably be ensured.
However, the STI technique forming a trench isolating region with a depth in accordance with the breakdown voltage results in the following new problem: a non-volatile memory generally comprises a memory cell and a peripheral circuit. The peripheral circuit includes a circuit requiring a high breakdown voltage (a high withstand circuit) and a logic circuit requiring a current drive capability but not a high breakdown voltage (a low withstand circuit). The high breakdown voltage circuit requires a breakdown voltage of a gate isolation film as well as the breakdown voltage between diffusion layers. Accordingly, the gate isolation film of a high breakdown voltage transistor requires a larger film thickness than the gate isolating film of a low breakdown voltage transistor. As a result, when the film thicknesses of the gate dielectric films required in the respective circuits are compared with one another, the gate isolating film of a high breakdown voltage transistor requires a larger film thickness than that of the memory cell transistor, while the required film thickness of the gate isolation film of the memory cell transistor is as large as or larger than that of the low breakdown voltage transistor.
A circuit for controlling the cell array of the non-volatile memory needs to be formed by high breakdown voltage transistors in order to control write of data onto the memory cell and deletion of data therefrom. Accordingly, the memory cell region (a region where a gate dielectric film of the memory cell is formed) is encompassed by the region of high breakdown voltage gate dielectric film.
In the above-described case, in order that the width of the trench isolating region may be reduced in the high breakdown voltage region or the insulation film of the high breakdown voltage circuit, a depth of the trench isolating region formed into a high breakdown voltage element is increased so that the breakdown voltage is ensured in the direction of depth, and, in the memory cell region (in the region where the gate isolation film of the memory cell is formed), a shallow trench isolating region is formed in order that the aspect ratio may be ensured with the width at which the breakdown voltage is ensured, whereupon the element region can be reduced.
In the prior art as shown in the foregoing document, a shallow trench isolating region with a small width is formed for the purpose of reduction in size in the high breakdown voltage element forming region or low breakdown voltage element forming electrode. However, since such consideration as described above is not given to a boundary region between the trench isolating regions, the width of the boundary region between the element forming regions is increased as the number of element forming regions is increased. Consequently, there is a definite limit in the reduction in the size of the semiconductor memory device.
Additionally, the prior art as shown in the foregoing document has the following defects in the fabricating process. FIGS. 24A and 24B explain the defects in the case where two types of trench isolating regions are provided. FIG. 24A typically shows the section of a boundary region 4 located between a memory cell region 2 and a high breakdown voltage circuit region 3 both formed on a silicon substrate 1.
A thin gate dielectric film 5 is formed on the memory cell region 2, whereas a thick gate dielectric film 6 is formed on the high breakdown voltage circuit region 3. A polycrystalline silicon film 7 and a chemical mechanical polishing (CMP) stopper film 8 are deposited on upper surfaces of the gate dielectric films 5 and 6 in turn. A shallow trench 9 (for forming a shallow trench isolating region) is formed in the memory cell region 2, whereas a deep trench 10 (for forming a deep trench isolating region) is formed in the high breakdown voltage circuit region 3. A doping agent 11 for isolating film is formed so as to cover the aforementioned films and trenches.
When two types of trench isolating regions having respective depths d1 and d2, the doping agent 11 needs to be deposited thick according to the deeper trench 10 in order that shallow and deep trenches 10 may be simultaneously embedded. In such a case, accordingly, the doping agent 11 is deposited so that its thickness Tcell in the shallow trench 9 is larger than its thickness THV in the deep trench 10 on the surface of the silicon substrate 1.
When a planarization process is carried out by the CMP method while the trenches have been doped with the doping agent 11, in order that the thick doping agent 11 deposited on the cell region 2 may be removed, the CMP process is carried out excessively by the difference in the film thickness for the doping agent 11 deposited on the peripheral deep trench 10 since the memory cell 2 side is smaller than the high breakdown voltage circuit region 3 side regarding the heights H1 and H2 from the surface of the stopper film 8 of the CMP to the surfaces of the trenches 9 and 10 respectively.
In such a case as described above, there is a possibility that the CMP process, when carried out, may cause dishing in the trench isolating region 12 formed in the boundary region 4 between the high breakdown voltage circuit region 3 and the memory cell region 2, resulting in a problem of abnormal shape. In particular, the width of the trench isolating region needs to be increased in the boundary region 4 since a well isolation is also carried out. Dishing D as shown in FIG. 24B tends to occur in the boundary region 4 between the memory cell region 2 and the high breakdown voltage circuit region 3 during CMP since the width of the trench isolating region is required to be increased for additional execution of well isolation, and the boundary region 4 is located between two regions of the peripheral region where the memory cell region 2 and the high breakdown voltage circuit region 3 both having different height distributions of the doping agent 11.
A dummy pattern is suggested to be disposed on an end of the cell array region to prevent dishing in order that an adverse effect of the dishing may be reduced. However, the number of dummy patterns needs to be increased with increase in the degree of dishing, whereupon a new problem arises that an area of the cell (or chip size) should be increased.
Furthermore, the process of doping the trenches 9 and 10 with a doping agent is carried out after formation of the gate dielectric films 5 and 6 in a self-aligned STI (SA-STI) process. In the SA-STI process, the difference in the height between the CMP stopper films 8 depends upon the difference in the film thickness between the gate dielectric films 5 and 6 of the memory cell region 2 and the high breakdown voltage circuit region 3 as well as the difference in the film thickness between the regions 2 and 3. This difference in the height between the CMP stopper films 8 also results in abnormal shape, such as erosion (dishing), scratch, etc., due to the CMP process in the boundary region 4 between the memory cell region 2 and the high breakdown voltage circuit region 3. Additionally, when the stopper film 8 is peeled by the dishing due to the CMP process in the memory cells of the cell array located in the vicinity of the boundary region 4, the height of the trench isolating region in the peeled portion is reduced, which reduction in the height results in various variations in the processing of memory cells and increases the variations in the electric characteristics of the memory cells.